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A DAC stage analog circuit generator for UDSM and FD-SOI technologies

: Prautsch, Benjamin; Rao, Sunil; Eichler, Uwe; Puppala, Ajith; Reich, Torsten

Fulltext urn:nbn:de:0011-n-3855611 (53 KByte PDF)
MD5 Fingerprint: 89ce9b7f7b88e6d93dd722e82218cbff
Created on: 21.2.2020

Fanucci, Luca (Chair) ; European Design Automation Association -EDAA-:
Design, Automation and Test in Europe Conference & Exhibition, DATE 2016. Proceedings : 14 - 18 March 2016, ICC, Dresden, Germany
Dresden, 2016
ISBN: 978-3-9815370-6-2
Paper UB07.9, 1 pp.
Design, Automation and Test in Europe Conference & Exhibition (DATE) <19, 2016, Dresden>
Bundesministerium für Bildung und Forschung BMBF
16ES0240; Things2Do
Thin but great Silicon to Design Objects
Conference Paper, Electronic Publication
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

The design of analog integrated circuits requires extensive manual work which is error-prone and inefficient. With advanced ultra-deep sub-micron (UDSM) technologies, the manual design effort increases further dramatically. This work presents the application of a rethought generator approach for the efficient reusable design of a 12 bit current steering DAC. The current mirror stage of the DAC, which is arranged in the complex Q² random walk scheme for high intrinsic matching [1], is realized by a circuit generator which automatically creates schematic, symbol, and layout of the required cells within few minutes. Originally focused on a 28 nm bulk technology, the generator code was also executed in a 28 nm FD-SOI technology with minor migration effort due to the generic nature of our tool. In addition, the fast circuit generation enables an efficient layout optimization showcasing the benefit of analog circuit generators for “bottom-up” design [2] in advanced technology nodes.