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Wafer level packaging for hermetical encapsulation of MEMS resonators

: Manier, Charles-Alix; Zoschke, Kai; Oppermann, Hermann; Ruffieux, D.; Piazza, S. dalla; Suni, T.; Dekker, J.; Allegato, G.


Benoit, Charlot; Mita, Yoshio; Nouet, Pascal; Pressecq, Francis; Schröpfer, Gerold; Rencz, Marta; Schneider, Peter ; Institute of Electrical and Electronics Engineers -IEEE-; IEEE Components, Packaging, and Manufacturing Technology Society:
DTIP 2015, 17th Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS : 27 - 30 April 2015, Montpellier, France
Piscataway, NJ: IEEE, 2015
ISBN: 978-1-4799-8627-9
ISBN: 978-1-4799-8545-6
ISBN: 978-1-4799-8625-5
Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS <17, 2015, Montpellier>
Conference Paper
Fraunhofer IZM ()

This paper will present wafer level packaging approaches and results for MEMS encapsulation and integration applied to resonators. The core technologies involve interposer fabrication with Through-Silicon Vias (TSV), temporary wafer bonding for thin wafer handling and wafer bonding for metallic sealing under vacuum and for formation of electrical interconnects. Seal rings based on AuSn metallurgy have been considered for process compatibility with MEMS and provide the hermetical sealing of the components after vacuum encapsulation. Different packaging processes were tested and are here succinctly presented for established quartz crystals as well as for emerging Silicon Resonators (SiRes). First investigations on if, and possibly how, wafer dicing affects the packaged components were performed. A yield of 80% could be achieved in wafer level packaging of quartz crystal resonators at 8'' wafer scale first step towards an ongoing 3D integration with CMOS.