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Hierarchical variability-aware compact models of 20nm bulk CMOS

: Wang, Xingsheng; Reid, D.; Wang, Liping; Burenkov, A.; Millar, C.; Lorenz, J.; Asenov, A.


Institute of Electrical and Electronics Engineers -IEEE-:
International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2015 : Washington, DC, USA, 9 - 11 September 2015
Piscataway, NJ: IEEE, 2015
ISBN: 978-1-4673-7858-1 (Print)
ISBN: 978-1-4673-7861-1
ISBN: 978-1-4673-7860-4
International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) <20, 2015, Washington/DC>
Conference Paper
Fraunhofer IISB ()

This paper presents a hierarchical variability-aware compact model methodology based on a comprehensive simulation study of global process variation and local statistical variability on 20nm bulk planar CMOS. The area dependence of statistical variability is carefully examined in the presence of random discrete dopants; gate line edge roughness; metal gate granularity; and their combination. Hierarchical variability-aware compact models have been developed, extracted and used to evaluate the impact of process variation and statistical variability on SRAM stability and performance.