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From fan-out wafer to fan-out panel level packaging

: Braun, Tanja; Becker, Karl-Friedrich; Raatz, Stefan; Bader, Volker; Bauer, Jochen; Aschenbrenner, Rolf; Voges, Steve; Thomas, Tina; Kahle, Ruben; Lang, Klaus-Dieter


Institute of Electrical and Electronics Engineers -IEEE-:
European Conference on Circuit Theory and Design, ECCTD 2015 : 24-26 August 2015, Trondheim, Norway
Piscataway, NJ: IEEE, 2015
ISBN: 978-1-4799-9877-7
4 pp.
European Conference on Circuit Theory and Design (ECCTD) <2015, Trondheim>
Conference Paper
Fraunhofer IZM ()

Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics for heterogeneous system integration. This paper describes the technological path from wafer level embedding to 24"times18" fan-out panel level packaging technology in combination with low cost PCB based RDL processes and discusses challenges and opportunities in detail. The technology described offers a cost effective packaging solution for various application as autonomous sensor nodes, packages for handheld consumer application or bio-medical application as sensor integration into microfluidics.