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Simulation and validation of arbitrary ordered VSCP-PLLs using event-driven macromodeling

: Ali, E.; Rahajandraibe, W.; Haddad, F.; Tall, N.; Hangmann, C.; Hedayat, C.


Institute of Electrical and Electronics Engineers -IEEE-; IEEE Circuits and Systems Society:
IEEE International Symposium on Circuits and Systems, ISCAS 2015. Proceedings. Vol.2 : 24-27 May 2015, Lisbon, Portugal
Piscataway, NJ: IEEE, 2015
ISBN: 978-1-4799-8392-6
ISBN: 978-1-4799-8391-9
ISBN: 978-1-4799-8390-2
International Symposium on Circuits and Systems (ISCAS) <2015, Lisbon>
Conference Paper
Fraunhofer ENAS ()

In modern electronic systems, PLLs are widely used for frequency synthesis applications. PLLs have a mixed analog-digital nature, which makes difficult to characterize its overall non-linear behavior using general theory of feedback system. To simulate the transient behavior of the PLL often the circuit level simulator is used. The frequency divider circuit separates the loop in low and high frequency parts leading to a small sampling time and a high simulation time, which are major technological bottlenecks using behavioral or transistor level models. In this paper, electrical simulations of an arbitrary ordered PLL operating with a voltage switched charge pump (VSCP) are performed. By simulating each block of the VSCP-PLL within the loop using transistor level model, the results were used to setup macroscopic parameters within the Event-Driven model. The Event-Driven simulation efficiently characterizes the off-locking transient domain in a very short time. The Event-Driven simulations are validated by transistor level simulations of arbitrary ordered integer-N VSCP-PLL designed in Cadence (Virtuoso) using CMOS technologies (130nm and 65nm).