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On the voltage scaling potential of SONOS non-volatile memory transistors

: Ocker, J.; Slesazeck, S.; Mikolajick, T.; Buschbeck, S.; Günther, S.; Yurchuk, E.; Hoffmann, R.; Beyer, V.


Pribyl, W. ; Institute of Electrical and Electronics Engineers -IEEE-; IEEE Electron Devices Society:
45th European Solid-State Device Research Conference, ESSDERC 2015. Proceedings : 14 - 18 September, Graz, Austria
Piscataway, NJ: IEEE, 2015
ISBN: 978-1-4673-7133-9 (Print)
ISBN: 978-1-4673-7135-3
ISBN: 978-1-4673-7134-6
ISBN: 978-1-4673-7471-2
European Solid-State Device Research Conference (ESSDERC) <45, 2015, Graz>
Conference Paper
Fraunhofer IPMS ()

With technology scaling of embedded nonvolatile memories, voltage scaling below 12 V is a primary goal to maintain the area efficiency of the memory module. The SONOS technology shows promise as a technology for present and future low voltage memory cells. This paper examines the physics of scaled SONOS gate dielectrics in relation to reducing the operational voltage. In particular, we have examined the influence of tunnel oxide, nitride and top oxide thicknesses. The results are supported by electrical simulation of the SONOS gate dielectric. By properly scaling the dielectric films and utilizing electrical simulation we have determined a limit for scalability of the SONOS technology in terms of operation voltage.