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Simplifying UVM in SystemC

: Vörtler, Thilo; Klotz, Thomas; Einwich, Karsten; Assmann, Felix

Design and Verification Conference & Exhibition Europe, DVCon Europe 2015. CD-ROM : November 11 - 12, 2015, Munich, Germany
Munich, 2015
5 pp.
Design and Verification Conference & Exhibition Europe (DVCon) <2015, Munich>
Conference Paper
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

UVM-SystemC is currently under standardization within Accellera with a first preview release expected in 2015. Although, the UVM standard is getting more and more language-agnostic with implementations available in e, SystemVerilog, and now SystemC, features for transaction-based stimulus and verification environment modeling still strongly rely on the underlying language. For example, packing, copying, and randomization operations are implemented differently in each of these languages; certain features such as aspect-oriented extensions of classes and methods are currently only available in e.