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Wafer-level chip size package (WL-CSP)

 
: Töpper, M.; Fehlberg, S.; Scherpinski, K.; Karduck, C.; Glaw, V.; Heinricht, K.; Coskina, P.; Ehrmann, O.; Reichl, H.

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IEEE transactions on advanced packaging 23 (2000), No.2, pp.233-238
ISSN: 1521-3323
English
Journal Article
Fraunhofer IZM ()

Abstract
Size reduction is one of the main driving forces for packaging in nearly all electronic applications. The interaction of size reduction with highest functionality and high reliability is also predominant for all microelectronic systems. Therefore a synergism of optimal product design, smallest single chip package and board technology will give the best solution. Wafer level CSP will be the best solution for single chip packaging matching all requirements for electronic systems and reducing total cost.

: http://publica.fraunhofer.de/documents/N-36886.html