Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

Smart PCBs manufacturing technologies

: Löher, T.; Neumann, A.; Böttcher, L.; Pahl, B.; Ostmann, A.; Aschenbrenner, R.; Reichl, H.


Wang, C. ; Institute of Electrical and Electronics Engineers -IEEE-:
ICEPT 2005, 6th International Conference on Electronics Packaging Technology 2005 : La Waterfront Hotel, Dameisha, Shenzhen, China, August 30 to September 2, 2005
Shenzhen, 2005
ISBN: 0-7803-9449-6
9 pp.
International Conference on Electronics Packaging Technology (ICEPT) <6, 2005, Shenzhen>
Conference Paper
Fraunhofer IZM ()

The inherent functionality of a printed wiring board can be dramatically increased by embedding electronic components into the board. For resistors, capacitors and inductors technological turnkey solutions are offered by major manufacturers and also novel technologies are under development. Application examples for passives integration into flexible PCBs will be given. A further boost of functionality will be accomplished by the integration of active chips into the board. An overview of different approaches and the respective sets of enabling technologies for the integration of chips into the board will be given. Two of the approaches for the chip integration into the board will be discussed in detail. A prerequisite for those technologies is the chip thinning, which is now available as a commercial service for chip thicknesses down to 20 µm. In the chip in polymer (CIP) approach the thin chip is precisely positioned and soundly attached onto the board surface. After lamination of a copper coated resin foil via contacts are drilled through the laminate to the contact pads of the chip. The transfer of precise chip position parameters with respect to the board is essential for this step. The wiring on the laminate foil to the chip and to other components is subsequently structured. Process parameters and results will be presented. For the embedding of chips into flexible PCBs the chip is flipped onto the substrate surface and thermode bonded. The process implies soldering. Therefore electroless Ni(P) is deposited onto the Al bond pads of the chip which is subsequently covered with small caps of solder. The solder cap heights are in the range of 4 to 8 µm in order to keep the interconnection height low. The solder joint is realized by thermode bonding of the chip onto the structured wiring of the substrate using no-flow underfiller. The chip containing layer is then laminated and contacted to outer layers of the board by conventional through hole technique. An assessment of the advantages and disadvantages of both approaches will be given on the status of our present understanding of the technological challenges.