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80 Gbit/s monolithically integrated clock and data recovery circuit with 1:2 DEMUX using InP-based DHBTs

80 Gbit/s monolithisch integrierte Takt- und Datenrückgewinnungsschaltung basierend auf einer InP-DHBT Technologie
: Makon, R.E.; Driad, R.; Schneider, K.; Ludwig, M.; Aidam, R.; Quay, R.; Schlechtweg, M.; Weimann, G.


Institute of Electrical and Electronics Engineers -IEEE-:
IEEE CSIC Symposium 2005 : IEEE Compound Semiconductor Integrated Circuit Symposium, 30 Oct. - 2 Nov. 2005
Piscataway, NJ: IEEE, 2005
ISBN: 0-7803-9250-7
Compound Semiconductor Integrated Circuit Symposium (CSIC) Symposium <27, 2005, Palm Springs/Calif.>
Conference Paper
Fraunhofer IAF ()
InP-DHBT; CDR; VCO; linear phase detector; linearer Phasendetektor; loop filter; Schleifenfilter

An 80 Gbit/s monolithically integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX) is reported. The integrated circuit (IC) is manufactured using an InP Double Heterostructure Bipolar Transistor (DHBT) technology which features cut-off frequency values of more than 220 GHz for both f(ind T) and f(ind max). The CDR circuit is mainly composed of a half-rate linear phase detector including an 1:2 DEMUX, a loop filter, and a voltage controlled oscillator (VCO). The 40 Gbit/s recovered and demultiplexed data for an 80 Gbit/s input signal feature a signal swing of approximately 600 mV(ind pp). The extracted 40 GHz clock signal shows a phase noise of -98 dBc/Hz at 100 KHz offset frequency. The corresponding peak-to-peak jitter amounts to 1.66 ps while the rms jitter is 0.37 ps. The full IC dissipates 1.65 W at a supply voltage of -4.8 V.