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Performance of a scaled Si gate n-well CMOS technology

: Zimmer, Günter; Fiedler, Horst-Lothar; Höfflinger, Bernd; Neubert, E.; Vogt, Holger


Electronics Letters 17 (1981), No.18, pp.666-667
ISSN: 0013-5194
Journal Article
Fraunhofer IMS ()
semiconductor devices and materials; metal-oxide semiconductor structures; metal-oxide semiconductor devices

A scaled n-well CMOS technology with 40 nm gate oxide, 1 µm PMOS and 2 µm NMOS transistors has been realised with peak effective mobilities of 710 and 260 cm2V-1s-1 for electrons and holes, respectively, and available voltage gains as high as 80 for a 1 µm PMOS and 115 for a 2 µm NMOS transistor. The corresponding maximum inverter gain was 75. The inverter supply voltage range was 1.5 to 12 V and the inverter delay time was 300 ps at 5 V supply voltage.