Extended event-driven modeling of a SD-fractional-N PLL including non-ideal effects

In modern systems PLLs are widely used e.g. for frequency synthesis. Since this feedback control system exhibits a mixed-signal nature, it is challenging to use general theory to characterize its dynamic behavior. Additionally, due to the low and high frequency parts, simulations utilizing either a behavioral or transistor-level model are not computer resource efficient. To overcome this the modular and enhanced Event-Driven Model can be used. Since the existing Event-Driven Model is neither applicable to take different divider delays into account nor to consider a SD-Modulator, this work focuses on the extension of this modeling approach considering a SD-Fractional-N PLL with non-ideal effects like dead zone, leakage current and different divider delays. This extended model is validated with transistor-level simulations and is used to explore the impact of non-ideal effects on the loop characteristics.