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High temperature 0.35 micron Silicon-on-Insulator CMOS technology

 
: Kappert, Holger; Dreiner, Stefan; Kordas, Norbert; Schmidt, Alexander; Paschen, Uwe; Kokozinski, Rainer

International Microelectronics and Packaging Society -IMAPS-:
International Conference and Exhibition on High Temperature Electronics, HiTEC 2014 : Albuquerque, New Mexico, USA, 13 - 15 May 2014
Red Hook, NY: Curran, 2014
ISBN: 978-1-63439-115-3
pp.254-258
International Conference and Exhibition on High Temperature Electronics (HiTEC) <2014, Albuquerque/NM>
English
Conference Paper
Fraunhofer IMS ()
high temperature; SOI; CMOS; 0.35 micron

Abstract
Silicon-on-Insulator (SOI) is the most commonly used technology for integrated circuits capable of operating at high temperature. Due to the efficient reduction of leakage current paths much higher operation temperatures are achievable with SOI than with bulk technologies. Published work on high temperature CMOS circuits typically refers to technologies with a minimum feature size of 0.8 to 1.0 micron [1] [2] [3] even though for complex digital circuits this results in large die size. Technologies with smaller feature size are available but typically not suitable for reliable high temperature operation due to high leakage currents, decreasing threshold voltages over temperature or reliability issues with the standard aluminum metallization.
Fraunhofer IMS has developed a high temperature 0.35 micron thin film SOI technology. The mixed signal technology provides numerous devices, e.g. specific transistors for analog and digital circuit design, diodes, resistors and voltage independent capacitors. Also non-volatile memory cells (EEPROM) are available. In addition the technology is equipped with a tungsten metallization for highly reliable operation even at high temperatures.
An overview on the new technology including characterization results of devices and test circuits is given in this paper.

: http://publica.fraunhofer.de/documents/N-322178.html