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2013
Conference Paper
Titel
Sequential hierarchical model-order reduction for robust design of parameter-varying systems
Abstract
In this paper we introduce a method for the hierarchical model order reduction of parameter-varying analog circuits. A new concept is presented that reduces the circuit's blocks to build a reduced overall model that does not violate a predefined error bound. An additional acceleration of the reduction process is achieved by introducing a sequential workflow of the reduction algorithm. Finally for illustration, we apply the overall procedure to the operational amplifier OpAmp 741 and compare it to the standard methods.