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Modeling and optimization of BiCMOS embedded through-silicon vias for RF-grounding

: Wietstruck, M.; Kaynak, M.; Marschmeyer, S.; Wipf, C.; Tekin, I.; Zoschke, K.; Tillack, B.


Institute of Electrical and Electronics Engineers -IEEE-:
IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2014 : 19-23 January 2014, Newport Beach, California
Piscataway, NJ: IEEE, 2014
ISBN: 978-1-4799-1523-1
ISBN: 978-1-4799-1520-0
ISBN: 978-1-4799-1521-7
Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) <14, 2014, Newport Beach/Calif.>
Conference Paper
Fraunhofer IZM ()

In this paper we demonstrate the modeling and optimization of BiCMOS embedded high aspect ratio through-silicon vias (TSV) for RF-grounding applications. The inductance and the resistance of the TSV are analyzed with respect to TSV design parameters and process effects such as sidewall-tilting and void formation. RF measurement results with extracted inductance and resistance of 24 pH and 86 m for a single TSV are in very good agreement with the simulation results. Based on the simulated and measured results, RLC-lumped-element models are developed considering the aforementioned process characteristics to provide realistic models for Process-Design-Kit (PDK) implementation.