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Novel layout and packaging for lateral, low-resistance GaN-on-Si power transistors

: Reiner, R.; Waltereit, P.; Benkhelifa, F.; Walcher, H.; Quay, R.; Schlechtweg, M.; Ambacher, O.

Energietechnische Gesellschaft -ETG-; European Center for Power Electronics -ECPE-:
CIPS 2014, 8th International Conference on Integrated Power Electronics Systems. Proceedings : February, 25-27, 2014 Nuremberg/Germany
Berlin: VDE-Verlag, 2014 (ETG-Fachbericht 141)
ISBN: 978-3-8007-3578-5
International Conference on Integrated Power Electronics Systems (CIPS) <8, 2014, Nuremberg>
Conference Paper
Fraunhofer IAF ()

This work introduces an innovative layout structure for lateral, low-resistance GaN-based power transistors, designed for use in TO220 packages. Design aspects for large gate width transistor structures of up to 359 mm and the inhomogeneous power distribution on active area and metallization of such structures are discussed. The new layout is realized using an AlGaN/GaN-on-Si technology. The devices are packaged and characterized. Results are directly compared to those obtained from a conventional comb structure. The fabricated device achieves drain currents of up to 90 A and on-state resistances as low as 50 m(omega).