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Front to backside alignment for TSV based 3D integration

: Windrich, F.; Schenke, A.


Institute of Electrical and Electronics Engineers -IEEE-:
IEEE International 3D Systems Integration Conference, 3DIC 2013 : 2-4 October 2013, San Francisco, Calif.
Piscataway, NJ: IEEE, 2013
ISBN: 978-1-4673-6484-3
6 pp.
International 3D Systems Integration Conference (3DIC) <2013, San Francisco/Calif.>
Conference Paper
Fraunhofer IZM ()

The demand of smaller form factors, multifunctional microelectronics and thereby the need for improved electrical performance and reliability is the key driver for the development of 3D technologies with through silicon vias (TSV). Different through silicon via approaches are available and have pros and cons regarding process integration. But in any case a front to backside alignment is necessary regardless if a via first, via middle or via last approach has been chosen. This paper discusses available alignment technologies and strategies which are needed for front to backside alignment on 3D TSV integration examples. Alignment results with a 300mm mask aligner for a 2.5D interposer application and a via last approach are shown. The top side overlay accuracy between filled through silicon vias and the next photoresist layer showed a variation of 3 sigma = 1.7 mu m. The overlay accuracy for the wafer backside between TSV and the first backside photoresist layer was doubled to 3 sigma = 3.4 mu m. The difference was caused by the used alignment method. Furthermore the influence of wafer deformation (warpage / bow) on backside alignment accuracy is discussed for an interposer application.