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Monte Carlo simulation using VHDL-AMS

: Wagner, Ekkehart-Peter; Haase, Joachim

Fulltext urn:nbn:de:0011-n-2870996 (253 KByte PDF)
MD5 Fingerprint: 895ecdddd3708698265deeba40229077
Created on: 29.4.2014

FDL 2004, Forum on Specification & Design Languages. Proceedings. Vol.1 : September 14-17, 2004, Lille
Lille, 2004
Forum on Specification & Design Languages (FDL) <7, 2004, Lille>
Conference Paper, Electronic Publication
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Monte Carlo simulation is widely used in Spice like circuit simulators. It allows to obtain statistical information derived from estimates of the random variability of circuit parameters. Multiple simulation runs are carried out with different sets of parameters. VHDL-AMS provides flexible possibilities to specify nominal and tolerance values and their distributions. Correlation between parameters can easily be taken into account. This is especially important if behavioral models are considered. The paper describes requirements and implementation aspects of the Monte Carlo simulation using VHDL-AMS.