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Solar cell efficiency losses due to impurities from the crucible in multicrystalline silicon

: Schindler, F.; Michl, B.; Schön, J.; Kwapil, W.; Warta, W.; Schubert, M.

Postprint urn:nbn:de:0011-n-2838640 (711 KByte PDF)
MD5 Fingerprint: ad188ae2ac678c09270c8795b4d0e3e8
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Created on: 25.4.2014

IEEE Journal of Photovoltaics 4 (2014), No.1, pp.122-129
ISSN: 2156-3381
ISSN: 2156-3403
Bundesministerium für Umwelt, Naturschutz, Bau und Reaktorsicherheit BMUB
0325270G; SolarWinS
Journal Article, Electronic Publication
Fraunhofer ISE ()
Solarzellen - Entwicklung und Charakterisierung; Silicium-Photovoltaik; Charakterisierung von Prozess- und Silicium-Materialien; Charakterisierung; Zellen und Module; silicon; Gettering; Lifetime; Efficiency Solar Cells; Deffects

The electrical material quality of multicrystalline (mc) silicon for photovoltaic applications suffers from crystal defects as well as from impurities that originate from the feedstock, the quartz crucible, and its coating. In this study, we investigate the influence of impurities from the crucible on efficiency losses in mc silicon solar cells, focusing on the limitation due to iron. The applicability of p-type mc silicon, crystallized in G1 sized crucibles of industrial material quality and very pure electrically fused silica, for a high-efficiency solar cell process is examined by measuring lifetime and interstitial iron concentration in the wafers after different processing steps and by estimating the cell efficiency potential from injection-dependent bulk lifetime measurements. Interstitial iron concentrations extracted from 2-D simulations of iron precipitation at crystal defects and gettering during processing agree well with Fei measurements at different process stages and explain the observations. Efficiency losses are quantified to losses due to segregated impurities diffused into the silicon melt, losses due to decorated crystal defects and losses due to solid-state diffusion into the crystal. By using a high-purity crucible, losses are reduced significantly and an efficiency gain of 0.5% absolute is estimated to be attainable on wafers with edge region.