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Vacuum packaging at wafer level for MEMS using gold-tin metallurgy

 
: Manier, C.-A.; Zoschke, K.; Oppermann, H.; Ruffieux, D.; Dalla Piazza, S.; Suni, T.; Dekker, J.; Allegato, G.

Institute of Electrical and Electronics Engineers -IEEE-:
European Microelectronics and Packaging Conference, EMPC 2013 : 9-12 September 2013, Grenoble, France
Piscataway, NJ: IEEE, 2013
ISBN: 978-2-95-274671-7
8 pp.
European Microelectronics and Packaging Conference (EMPC) <2013, Grenoble>
English
Conference Paper
Fraunhofer IZM ()

Abstract
Results of wafer level packaging for micro-electro-mechanical systems based on low temperature melting metallurgy are going to be presented. The MEMS are packaged under vacuum with internal pressure in the range of 1 mbar after sealing. Through Silicon Vias in a silicon interposer allow the feeding of the electrical contacts to the package outside. The thin silicon interposer acts as MEMS carrier or lid and therefore is part of the final packaged component after dicing. AuSn rings have been chosen for process compatibility with the MEMS and ensure the hermeticity of the components after vacuum sealing. Evaluation of the bond process is carried out using XRay imaging microscopy, analysis of cross sections and the final package resistance is evaluated using shear testing. The thickness of the chip-scale packaged MEMS is smaller than 500 mu m and a yield of vacuum sealing of around 80% was obtained in first evaluation on 200 mm wafer scale.

: http://publica.fraunhofer.de/documents/N-282039.html