The method involves providing (14) a substrate (16) i.e. silicon wafer, with multiple integrated circuit portions (18a, 18b), which are arranged at predetermined positions. Multiple isolated components (22a, 22b) are applied (20) on another substrate (24). The substrates are placed such that contact surfaces (K22a, K22b) of the isolated components are aligned with the predetermined positions of the circuit portions. The contact surfaces of the isolated components are connected (28) with the circuit portions. The latter substrate is removed (30) from the isolated components.