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Crack and delamination risk evaluation of thin silicon based microelectronics devices

: Auersperg, J.; Vogel, D.; Michel, B.

11th International Conference on Fracture 2005, ICF11. Vol.5 : Proceedings of a meeting held 20-25 March 2005, Turin, Italy
Red Hook, NY: Curran, 2005
ISBN: 978-1-617-82063-2
International Conference on Fracture <11, 2005, Turin>
Conference Paper
Fraunhofer IZM ()

Enhancing miniaturization and system integration of microelectronics components demands growingly for novel solutions toward embedding active and passive components into substrates, clothes, protective sleeves of consumer goods - smart, thin applications in general. As a result, the embedding of very thin silicon dies and metallic structures into highly flexible polymeric, paper like or textile materials causes several mechanical problems preventing those applications from being utilized. Various kinds of inhomogeneity, residual stresses from several steps of the manufacturing process contribute to interface delaminations, chip cracking and fatigue of solder interconnects. This paper intends to demonstrate and discuss advantages and needs of using fully parameterized modeling techniques for design optimizations of thin devices on the basis of nonlinear finite element simulations. These numerical investigations take into account the nonlinear, temperature and rate depend ent behavior of the different materials used and the application of advanced fracture mechanics concepts (energy release rate, integral fracture approaches, mode-mixity examinations) with regards to the specific area of surface-near and interface-near micro scaled regions. For improving the utilized methodology, the evaluation of mixed mode interface delamination phenomena and fracture were combined with experimental investigations by means of SEM and AFM.