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A new method to determine the tool count of a semiconductor factory using FabSim

 
: Vogt, H.

:
Fulltext (PDF; - Externer Link)

Ingalls, R.G. ; Institute of Electrical and Electronics Engineers -IEEE-:
Winter Simulation Conference, WSC 2004. Proceedings. Vol.2 : Washington Hilton and Towers, Washington, D.C., U.S.A., December 5 - 8, 2004
New York, NY: IEEE, 2004
ISBN: 0-7803-8786-4
ISBN: 0-7803-8787-2
pp.1925-1929
Winter Simulation Conference (WSC) <36, 2004, Washington/DC>
English
Conference Paper, Electronic Publication
Fraunhofer IMS ()
FabSim; fab simulator; Simulation; Fertigung; Software-Tool; Halbleiterfertigung

Abstract
Tool count optimization is mandatory for an efficiently organized semiconductor factory. This paper describes an efficient heuristic to determine the tool count using the compact fab simulator FabSim Interactive. A combination of the Simulated Annealing algorithm and the knowledge of toolset usage, which is gained by repeated simulation of the factory, results in a fast approach. There are no restrictions concerning multiple products and processes during optimization. A simple cost model (revenue per wafer out minus tool depreciation) yields the objective function to be maximized, tool count values per toolset are the decision variables, and a lot start sequence determines the fab throughput required. Depending on the factory size, optimization results may be available within a few hours of simulation time on a standard PC.

: http://publica.fraunhofer.de/documents/N-26116.html