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A flexible approach for compiling scilab to reconfigurable multi-core embedded systems

: Stripf, T.; Oey, O.; Bruckschloegl, T.; Koenig, R.; Huebner, M.; Becker, J.; Rauwerda, G.; Sunesen, K.; Kavvadias, N.; Dimitroulakos, G.; Masselos, K.; Kritharidis, D.; Mitas, N.; Goulas, G.; Alefragis, P.; Voros, N.S.; Derrien, S.; Menard, D.; Sentieys, O.; Goehringer, D.; Perschke, T.


Soares Indrusiak, L. ; Institute of Electrical and Electronics Engineers -IEEE-:
7th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2012 : York, United Kingdom, July 9-11, 2012. Proceedings
Piscataway, NJ: IEEE, 2012
ISBN: 978-1-4673-2572-1
ISBN: 978-1-4673-2570-7
International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) <7, 2012, York>
Conference Paper
Fraunhofer IOSB ()

The mapping process of high performance embedded applications to today's reconfigurable multiprocessor System-on-Chip devices suffers from a complex toolchain and programming process. Thus, the efficient programming of such architectures in terms of achievable performance and power consumption is limited to experts only. Enabling them to nonexperts requires a simplified programming process that hides the complexity of the underlying hardware - introduced by software parallelism of multiple cores and the flexibility of reconfigurable architectures - to the end user. The Architecture oriented paraLlelization for high performance embedded Multi-core systems using scilAb (ALMA) European project aims to bridge these hurdles through the introduction and exploitation of a Scilab- and architecture-description-language-based toolchain which enables the efficient mapping of applications on multiprocessor platforms from high level of abstraction. This holistic solution of the tool chain allows the complexity of both the application and the architecture to be hidden, which leads to a better acceptance, reduced development costs, and shorter time-to-market.