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Through mold via technology for multi-sensor stacking

 
: Braun, T.; Brundel, M.; Becker, K.-F.; Kahle, R.; Piefke, K.; Scholz, U.; Haag, F.; Bader, V.; Voges, S.; Thomas, T.; Aschenbrenner, R.; Lang, K.-D.

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Institute of Electrical and Electronics Engineers -IEEE-; IEEE Components, Packaging, and Manufacturing Technology Society:
IEEE 14th Electronics Packaging Technology Conference, EPTC 2012. Proceedings : 5 - 7 December 2012, Resort World Sentosa, Singapore
New York, NY: IEEE, 2012
ISBN: 978-1-4673-4553-8 (Print)
ISBN: 978-1-4673-4551-4 (Online)
pp.316-321
Electronics Packaging Technology Conference (EPTC) <14, 2012, Singapore>
English
Conference Paper
Fraunhofer IZM ()

Abstract
With the increasing market of handheld electronics e.g. smartphones and tablet PCs also an increasing demand for highly miniaturized multi-sensor packages shows up. One application scenario here would be an electronic compass allowing indoor navigation in complex buildings with a smartphone. These applications of highly miniaturized heterogeneous system integration lead to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding is one major packaging trend in this area. This paper describes the use of advanced molding techniques for multi-chip embedding in combination with large area and low cost redistribution technology derived from printed circuit board manufacturing with focus on integration of through mold vias for package stacking. The use of compression molding equipment with liquid or granular epoxy molding compounds for the targeted integration process fl ow is a technological approach that has been developed to allow large area embedding of single chips but also of multiple chips or heterogeneous systems on wafer scale. Embedding area today is typically in the size range of 8' to 12' in diameter, while future developments will deal with panel sizes up to 470 × 370 mm2;. The wiring of the embedded components in this novel type of SiP is done using PCB manufacturing technologies, i.e. a resin coated copper (RCC) film is laminated over the embedded components - whichever no matter which shape they are: a compression molded wafer or a larger rectangular area or a Molded Array Package (MAP). Interconnects are formed by laser drilling to die pads and electroplating - all of them making use of standard PCB processes. Also through vias for z-axis interconnection, a standard features in PCB manufacturing, can be integrated in the proposed process flow for mold embedding in combination with RCC based redistribution. These vias were laser drilled after RCC lam

: http://publica.fraunhofer.de/documents/N-254102.html