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Design methodology for CMOS frequency-synthesizers for low-power low-cost FSK-transceivers

 
: Christoffers, N.; Kolnsberg, S.; Kokozinski, R.; Stücke, T.; Hosticka, B.J.

Wireless Congress 2004. Systems & Applications. Conference proceedings
München: Electronica, 2004
Wireless Congress <2004, München>
English
Conference Paper
Fraunhofer IMS ()
Sigma-Delta-Fractional-N; frequency synthesis; settling time; spurious emission; Gm-C-biquads; Frequenzsynthese; Ausregelzeit; Störstrahlung

Abstract
CMOS wireless digital transceivers using frequency-shift-keying (FSK) can operate at low power consumption and chip area for several reasons: relaxed linearity requirement of the power amplifier due to constant envelope, simplicity of noncoherent IF receivers based on a frequency discriminator, and further. Overall FSK is a candidate for use in low power and low cost wireless communication systems. Consider, for example, Bluetooth, GSM, or customer-tailored low power wireless networks (e.g. sensor networks). The frequency synthesizer in an FSK-transceiver contributes to a further decrease of power consumption if it is modulatable. Thereby it obiviates the need of power hungry upconversion mixers. Unfortunately, the only viable synthesizer-type for this application is a so called Sigma-Delta-fractional-N-synthesizer. The design of this is very complex due to stability issues and a difficult tradeoff between spurious emmissions and settling time. However, our novel design methodology, proposed in this lecture, handles it quite easily. It employs a direct synthesis of the loop-filter-transfer function from the closed-loop-function. It exploits strong resemblance of numerical optimization results in spite of strongly varying requirements. And it attaches the loop-filter with a low-noise, low power consumption and low chip-area Gm-C-biquad.

: http://publica.fraunhofer.de/documents/N-25374.html