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A flow for parasitics extraction in 3D-systems

: Heinig, Andy; Dittrich, Michael; Reitz, Sven; Stolle, Jörn

Preprint urn:nbn:de:0011-n-2467709 (648 KByte PDF)
MD5 Fingerprint: 8a7a6d21dbaa1e42663beabc60f5d6ae
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Created on: 1.8.2014

Schmidt, Georg (Ed.) ; Institute of Electrical and Electronics Engineers -IEEE-:
International Semiconductor Conference Dresden-Grenoble, ISCDG 2012 : Grenoble, France, 24 - 26 September 2012; Technology, design, packaging, simulation and test ; international conference, short course and table-top exhibition
New York, NY: IEEE, 2012
ISBN: 978-1-4673-1717-7 (Print)
International Semiconductor Conference Dresden-Grenoble (ISCDG) <2012, Grenoble>
Conference Paper, Electronic Publication
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
parasitics extraction; 3D-systems; capacitance; STEP; XML

Due to high integration density in 3D-Systems parasitic effects, which are originally not taken into account during design-phase, has a growing influence on the behavior of the entire system. Therefore, the influences of these effects have to be minimized within the design process. In the following a hierarchical modeling based flow for parasitic extraction of capacitance in 3D-Systems is described. The flow contains layout data import, translation and export data to our own hierarchical XML-based description, and electromagnetic calculations for capacitance extraction.