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Closing the gap between systemC/AMS simulation and lab-based validation

Presentation held at edaWorkshop 2013, Dresden, May 14-16, 2013
: Vörtler, Thilo; Arndt, Thomas; Einwich, Karsten

presentation urn:nbn:de:0011-n-2447709 (1.8 MByte PDF)
MD5 Fingerprint: 5d1573548c097364e28dfa1e118e9af6
Created on: 26.6.2013

2013, 13 Folien
edaWorkshop <7, 2013, Dresden>
European Commission EC
FP7-ICT; 287562; VERDI
Presentation, Electronic Publication
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

The European Framework 7 project called VERDI (Verification for heterogeneous reliable design and integration started more than one year ago to address the verification and validation (V&V) challenges related to heterogeneous and mixed-signal system design and integration. The VERDI project is currently developing a unified system-level V&V methodology, using industry-recognized standards such as UVM, SystemC/-AMS, and IP-XACT. In this talk, first results of the V&V methodology will be presented with a special focus on how verification scenarios can be reused in the hardware validation phase.