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Via last technology for direct stacking of processor and flash

 
: Puschmann, R.; Bottcher, M.; Ziesmann, M.; Bartusseck, I.; Windrich, F.; Fiedler, C.; John, P.; Manier, C.; Zoschke, K.; Grafe, J.; Oppermann, H.; Wolf, M.J.; Lang, K.D.

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Institute of Electrical and Electronics Engineers -IEEE-:
IEEE 62nd Electronic Components and Technology Conference, ECTC 2012 : May 29 2012-June 1 2012, San Diego, CA
New York, NY: IEEE, 2012
ISBN: 978-1-4673-1966-9 (Print)
ISBN: 978-1-4673-1964-5 (Online)
pp.1327-1332
Electronic Components and Technology Conference (ECTC) <62, 2012, San Diego/Calif.>
English
Conference Paper
Fraunhofer IZM ()

Abstract
Some mobile applications require non volatile memories and very small spatial dimensions. The investigation results discussed in this paper are related to a via-last TSV integration scheme where a standard flash memory is connected to the backside of a processor chip (PC) using the through silicon via (TSV) technology. Special focus was given to the realization of chip interconnects between processor chip and the memory. This paper presents the process of the TSV formation starting with a photo resist deposition till TSV fill realized by electro-chemical copper deposition (ECD) and briefly the manufacturing of the redistribution layers as well the die-to-wafer (D2W) assembly of the flash chips. Electrical results will be presented showing the quality of the TSV isolation, the effect of the TSVs on its adjacencies and the quality of the interconnects for the case of flash chips attached to the frontside of the processor wafer (PW).

: http://publica.fraunhofer.de/documents/N-223408.html