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Thermal management in the design space exploration of 3D stacks and corresponding package

: Heinig, Andy; Knöchel, Uwe; Schneider, Peter; Wilde, Andreas

European Congress on Computational Methods in Applied Sciences and Engineering, ECCOMAS 2012. Proceedings. CD-ROM : September 10-14, 2012, Vienna, Austria; Abstractband
Vienna: Vienna University of Technology, 2012
ISBN: 978-3-9502481-8-0 (Abstract-Band)
ISBN: 978-3-9502481-9-7 (CD-ROM)
ISBN: 9783950353709
12 pp.
European Congress on Computational Methods in Applied Sciences and Engineering (ECCOMAS) <6, 2012, Vienna>
Conference Paper
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
3D integration; thermal management; design space exploration; chip-package-board-codesign

The stacking of dies allows a dense integration of electronic systems, which enables new applications especially for smart systems. Even though 3D integration allows reducing power consumption, the heat transfer must be ensured, as the power dissipation per volume increases. Thermal problems could be solved most efficient, if they are identified at early design levels. The right positioning of modules with higher and lower power dissipation in a stack in combination with structures that provide thermal conductivity can avoid hotspots in a design and helps to fulfill thermal specification. In the presented approach the design space exploration (DSE) algorithm generates and evaluates different architectures of a 3D system in order to identify the cost and performance efficient candidates. A new constructive solid geometry based language, is used to describe the system geometry at this design level. A new developed octree based finite difference method (FDM) is used to calculate efficient the heat distribution across the stack. As the temperature calculation must be executed many times during optimization, a trade-off between accuracy and run-time is needed. The accuracy of the thermal analysis will be controlled by the DSE. At the beginning of optimization a high number of candidates will be analyzed fast with moderate accuracy. In later steps more precise heat maps are computed for a few most promising architectures.