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Applying electric fault simulation for deriving tests for through-silicon vias

 
: Gulbins, Matthias; Hopsch, Fabian; Schneider, Peter; Straube, Bernd; Vermeiren, Wolfgang

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Postprint urn:nbn:de:0011-n-2114681 (226 KByte PDF)
MD5 Fingerprint: 1ee56f37b5dd91dc2608a8b592bb754d
© 2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Created on: 16.8.2012


IEEE Computer Society:
First IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, 3D-TEST 2010 : In conjunction with ITC / Test Week 2010; Convention Center - Austin, Texas, USA; 4. + 5. November 2010
New York, NY: IEEE, 2010
6 pp.
International Workshop on Testing Three-Dimensional Stacked Integrated Circuits <1, 2010, Austin/Tex.>
International Test Conference (ITC) <2010, Austin/Tex.>
English
Conference Paper, Electronic Publication
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
3D IC testing; TSV test; defect-oriented testing; fault simulation requirements; electric fault simulation

Abstract
Through-silicon vias (TSVs) present new, essential elements within 3D stacked Integrated Circuits (IC). Since they connect different layers of 3D stacks, their proper operation is an essential prerequisite for the system function. In this paper a procedure for deriving local digital test sequences for TSVs is presented. The behavior of TSVs including their typical surrounding circuitry is investigated under the impact of assumed faults using fault simulation. Since a purely digital consideration of faulty behavior of TSVs is not sufficient, the TSVs have to be modeled and analyzed at electrical level. The TSVs are embedded by inverters used as drivers at the inputs and buffers at the outputs. All mentioned elements are described at electrical level by spice-like netlists. By an analogue fault simulation tool faults are injected into this electric network model. The simulations of the so modified networks were running in parallel on a compute cluster including the evaluations of the fault effects. The fault simulations are carried out automatically. The test signals needed for fault detection are concatenated to form a digital TSV test sequence.

: http://publica.fraunhofer.de/documents/N-211468.html