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FPGA-based image combiner for parallel rendering

: Winzker, M.; Schwandt, A.; Hinkenjann, A.; Maiero, J.; Bues, M.


Institute of Electrical and Electronics Engineers -IEEE-, Malaysia Section:
IEEE International Conference on Signal and Image Processing Applications, ICSIPA 2011 : Kuala Lumpur, Malaysia, 16 - 18 November 2011
Piscataway: IEEE, 2011
ISBN: 978-1-4577-0241-9 (print)
ISBN: 978-1-4577-0243-3
International Conference on Signal and Image Processing Applications (ICSIPA) <2, 2011, Kuala Lumpur>
Conference Paper
Fraunhofer IAO ()

Rendering of virtual scenes is an application that still demands higher computing power for more complex and more realistic scenes. In addition to existing parallel processing inside a graphics processing unit, this paper investigates a further level of parallelization. A combiner based on an FPGA (field programmable gate array) allows to merge the graphics output of several independent computers. The image combiner supports different load distribution techniques, namely sort-first and sort-last rendering. A system prototype based on a commercial evaluation system proved the viability of the approach. A compact and cost-efficient dedicated implementation has been designed and is used as a platform to investigate different approaches for parallel rendering.