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Path-based statistical gate-level analyses considering timing and energy

: Lange, André; Hopsch, Fabian; Haase, Joachim

Preprint urn:nbn:de:0011-n-2055141 (279 KByte PDF)
MD5 Fingerprint: 642ba753a780b0ceafa451295f298ba7
Created on: 6.8.2014

Verband Deutscher Elektrotechniker e.V. -VDE-, Berlin:
PRIME 2012, 8th Conference on Ph.D. Research in Microelectronics & Electronics. CD-ROM : 12-15 June 2012,RWTH Aachen University Germany; Madonna di Campiglio, Trento - Italy
Berlin: VDE-Verlag, 2012
ISBN: 978-3-8007-3442-9
Conference on Ph.D. Research in Microelectronics & Electronics (PRIME) <8, 2012, Aachen>
Conference Paper, Electronic Publication
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Global and local fluctuations in leading-edge semiconductor manufacturing affect today's integrated circuits. While the former had been known and counteracted for years already, the latter arose when moving device dimensions into the deep submicron regime. In industrial digital circuit design, global and local variations are considered separately by process corners and on-chip variations. Both approaches have been criticized being inaccurate. As an alternative, for instance Statistical Static Timing Analysis applies analytical standard cell models to handle variability on gate level. We think, however, that multivariate statistical models may be an attractive solution as well since they may combine information on timing and power. In this paper, we propose a fully statistical approach for standard cell modelling and its application in statistical gate-level analyses combining propagation delay and energy consumption for timing paths. Using 45-nm predictive technology models, our gate-level results are close to SPICE reference simulations. Nevertheless, further research on statistical standard cell modeling is required on the way towards statistical analyses of complete digital blocks.