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3D stacking approaches for mold embedded packages

 
: Braun, Tanja; Becker, Karl-F.; Voges, Steve; Thomas, Tina; Töpper, Michael; Fischer, Thorsten; Kahle, Ruben; Bader, Volker; Bauer, Jörg; Aschenbrenner, Rolf; Lang, Klaus-Dieter

International Microelectronics and Packaging Society -IMAPS-; Institute of Electrical and Electronics Engineers -IEEE-:
18th European Microelectronics and Packaging Conference, EMPC 2011. Proceedings. CD-ROM : Brighton, 12th-15th September 2011
Andover, Hampshire: IMAPS UK, 2011
ISBN: 978-0-9568086-0-8
ISBN: 978-1-4673-0694-2 (Print)
European Microelectronics and Packaging Conference (EMPC) <18, 2011, Brighton>
English
Conference Paper
Fraunhofer IZM ()

Abstract
The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding technologies and embedding of active components into printed circuit boards (Chip-in-Polymer) are two major packaging trends in this area.
This paper describes the use of a novel S2iP (Stacked System in Package) interconnect technique using advanced molding process for multi chip embedding in combination with large area and low cost redistribution technology derived from printed circuit board manufacturing with a focus on integration of through mold vias and vertical interconnect elements for package stacking.
The use of compression molding equipment with liquid or granular epoxy molding compounds for the targeted integration process flow is a new technology that has been especially developed to allow large area embedding of single chips but also of multiple chips or heterogeneous systems on wafer scale, typically 8? to 12?. The wiring of the embedded components in this novel type of SiP can be done using PCB manufacturing technologies, i.e. a resin coated copper (RCC) film is laminated over the embedded components. Also thin film redistribution technologies can be applied ? using similar processes as used for WLP on silicon. For the 3D interconnection two technologies are evaluated: In a process flow similar to conventional PCB manufacturing vias are drilled using a UV laser after RCC lamination and are metalized in the same process as the vias for chip interconnection. A second via generation process uses vertical interconnect elements, e.g. silicon dies with well defined lead structures, assembled in the same process step as the embedded dies. Top and bottom surface of those vertical interconnect elements are exposed after mold embedding. Planar interconnection is then formed by thin film redistribution or after RCC lamination, the vertical interconnect elements are contacted using a µVia process.
Within this study the different approaches to vertical interconnection in a mold embedded wafer have been intensively evaluated on their processability. A strong focus was put on the process chain chip placement on a temporary carrier - compression vacuum molding for embedding ? RCC lamination or thin film redistribution ? laser drilling processes for µVias & Thru Holes ? metallization structuring ? module singulation & 3D assembly. The feasibility of the entire process chain is demonstrated by fabrication of a Ball Grid Array (BGA) type of system package with two embedded dies and through mold vias allowing the stacking of these BGA packages. Reliability of the manufactured 3D stacks is evaluated by temperature cycling and is analyzed both non-destructively and destructively.
The paper depicts a final technology demonstrator where two BGAs are stacked on each other and mounted on a base substrate enabling the electrical connection of the stacked module, allowing the evaluation of the technology and the applied processes.

: http://publica.fraunhofer.de/documents/N-195510.html