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Technologies and Trends to Improve Power Electronic Packaging

 
: Schneider-Ramelow, Martin; Hutter, Matthias; Oppermann, Hermann; Göhre, Jens-Martin; Schmitz, Stefan; Hoene, Eckart; Lang, Klaus-Dieter

International Microelectronics and Packaging Society -IMAPS-:
IMAPS 2011, 44th International Symposium on Microelectronics. Proceedings. Vol.1 : Long Beach, California, USA, 9 - 13 October 2011
Red Hook, NY: Curran, 2012
ISBN: 978-1-618-39850-5
pp.430-437
International Symposium on Microelectronics (IMAPS) <44, 2011, Long Beach/Calif.>
English
Conference Paper
Fraunhofer IZM ()

Abstract
In the realm of power modules a strong trend toward high temperature and high reliability ap-plications can be observed, which entails new technological challenges, especially for the assembly and packaging of power semiconductors. Because of the well known failure mechanisms of established lead-free standard soldering and heavy aluminum wire bonding technologies, such as fatigue and creep of die attach material and wire bonds at thermal cycling, academic and industrial research focuses on more reliable interconnection technologies. A priority is the research of alternative top and bottom side chip interconnection-materials or technologies to improve the temperature cycling strength of power chips typically assembled on ceramic substrates. The scientific focus is on Ag sintering as die attach and/or heavy ribbon bonding, for example with Al or bi-metal (Al-Cu). Our paper discusses the relevance of powder shape and size for the reduction of process pressure and temperature. Another focus are the material behavior of ribbon bonds in combination with bonding machine improvements (higher bonding parameters, cutting tool). But there are other very promising technologies like transient liquid phase bonding, for example with Cu-Sn or Ag-Sn systems or Cu heavy wire bonding (up to 400 µm wire diameter). Challenges posed by these technologies have to be discussed focusing on materials and process selection and reliability issues. Process temperatures and temperature profiles must be optimized, wire bonding machines and the chip surface structures as well as finish metallizations need to be adapted. The presentation will give an overview of alternative power chip interconnection technologies and discuss the challenges related to processing and reliability.

: http://publica.fraunhofer.de/documents/N-191071.html