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Processing of ultrathin 300 mm wafers with carrierless technology

: Spiller, S.; Molina, F.; Wolf, J.M.; Grafe, J.; Schenke, A.; Toennies, D.; Hennemeyer, M.; Tabuchi, T.; Auer, H.


IEEE Components, Packaging, and Manufacturing Technology Society:
IEEE 61st Electronic Components and Technology Conference, ECTC 2011 : Lake Buena Vista, Florida, USA, 31 May - 3 June 2011; 2011 proceedings
Piscataway/NJ: IEEE, 2011
ISBN: 978-1-61284-497-8 (Print)
ISBN: 978-1-61284-498-5
ISBN: 978-1-61284-496-1
Electronic Components and Technology Conference (ECTC) <61, 2011, Lake Buena Vista/Fla.>
Conference Paper
Fraunhofer IZM ()

We present a "carrierless" design for the manufacturing of ultrathin Silicon wafers, which are used in e.g. TSV (Through Silicon Via) and power chip applications. A carrierless wafer is a wafer which has a thinned inner portion, usually thinner than 150 m, and a rim portion, which is stabilizing the wafer, so that the whole wafer can be handled without any additional support. In more detail, progress on 300 mm carrierless wafers and its compatibility with standard applications like RDL (Redistribution Layer) and bumping will be discussed.