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TSV based silicon interposer technology for wafer level fabrication of 3D SiP modules

: Zoschke, K.; Wolf, J.; Lopper, C.; Kuna, I.; Jurgensen, N.; Glaw, V.; Samulewicz, K.; Roder, J.; Wilke, M.; Wunsch, O.; Klein, M.; Suchodoletz, M.V.; Oppermann, H.; Braun, T.; Wieland, R.; Ehrmann, O.


IEEE Components, Packaging, and Manufacturing Technology Society:
IEEE 61st Electronic Components and Technology Conference, ECTC 2011 : Lake Buena Vista, Florida, USA, 31 May - 3 June 2011; 2011 proceedings
Piscataway/NJ: IEEE, 2011
ISBN: 978-1-61284-497-8 (Print)
ISBN: 978-1-61284-498-5
ISBN: 978-1-61284-496-1
Electronic Components and Technology Conference (ECTC) <61, 2011, Lake Buena Vista/Fla.>
Conference Paper
Fraunhofer EMFT ()
Fraunhofer IZM ()

Silicon interposers with through silicon vias (TSVs) have become important key components of 3D architectures. They are used as intermediate carrier and wiring device for IC components like logics, memories and sensors. Due to custom specific front and back side wiring interposers enable to adapt the fine pitch IO terminals of the mounted ICs to the IO geometries of the package level. High density copper filled TSVs with high aspect ratio as well as high density multi layer wiring using electro plated copper as conductive material and low loss dielectrics enable high performance signal transmission at interposer level without serious losses by parasitic effects. This paper presents the fabrication steps for wafer level processing of silicon interposers with copper filled TSVs as well as their wafer level assembly with IC components. Special focus is drawn on the TSV formation process including via etching, isolation and filling as well as front side high density wiring and subsequent backside processing of the thin TSV wafers. In this context, also temporary wafer to wafer bonding which is required for backside processing of thin TSV wafers is discussed. The final interposers which carry one or more IC components have lateral dimensions up to several square centimeters and thicknesses between 50-100 m. They include up to several thousands of TSVs per device with a single electrical resistance between 4.9-5.7 mOhms. All processes were run using production equipment at 200 mm wafers.