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Simulation-based evaluation of the ramp-up behavior of waferfabs

: Sturm, R.; Dorner, J.; Reddig, K.; Seidelmann, J.


Graef, M. ; Semiconductor Equipment and Materials International -SEMI-, San Jose/Calif.; Institute of Electrical and Electronics Engineers -IEEE-:
ASMC 2003, the 14th annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop. Proceedings : Advancing the science of semiconductor manufacturing excellence
Piscataway, NJ: IEEE, 2003
ISBN: 0-7803-7673-0
Advanced Semiconductor Manufacturing Conference and Workshop (ASMC) <14, 2003, München>
Conference Paper
Fraunhofer IPA ()
wafer; ramp up; Fertigungsanlauf; Simulation; Halbleiter; Fertigung

In this paper we present a simulation study of wafer fab ramp-up scenarios with the simulation software AutoSched AP. A generic factory model (MIMAC 1 from Int. SEMATECH) was adapted to simulate fab ramp-up scenarios. The model was customized to consider time phased modeling capability and time phased reporting. Additionally, an evaluation approach for the comparison of different ramp-up scenarios is presented. This approach helps to evaluate the ramp-up performance with different input parameters. A systematic variation of dispatch rules and lot sizes during ramp-up is shown.