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GePaRD - A High-Level generation flow for Partially Reconfigurable designs

: Boden, M.; Fiebig, T.; Reiband, M.; Reichel, P.; Rülke, S.


Torres, L.:
IEEE Computer Society Annual Symposium on VLSI, ISVLSI '08
Los Alamitos: IEEE Computer Society, 2008
ISBN: 978-0-7695-3170-0
ISBN: 978-0-7695-3291-2 (print)
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) <2008, Montpellier>
Conference Paper
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

This paper presents GePaRD, a novel approach to High-Level Synthesis of self-adaptive systems based on Partially Reconfigurable (PR) FPGAs. GePaRD combines Temporal Modularization and Temporal Placement in order to reduce the reconfiguration overhead at runtime by extracting Temporal Reusable Modules. We introduce the basics of High-Level PR design as well as the GePaRD design steps (transformations) and GePaRD descriptions (models). Moreover, we describe our approach to Temporal Modularization using Greedy Clique Partitioning and Temporal Placement using Simulated Annealing.