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Through mold vias for stacking of mold embedded packages

 
: Braun, T.; Becker, K.-F.; Voges, S.; Thomas, T.; Kahle, R.; Bader, V.; Bauer, J.; Piefke, K.; Krüger, R.; Aschenbrenner, R.; Lang, K.-D.

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IEEE Components, Packaging, and Manufacturing Technology Society:
IEEE 61st Electronic Components and Technology Conference, ECTC 2011 : Lake Buena Vista, Florida, USA, 31 May - 3 June 2011; 2011 proceedings
Piscataway/NJ: IEEE, 2011
ISBN: 978-1-61284-497-8 (Print)
ISBN: 978-1-61284-498-5
ISBN: 978-1-61284-496-1
pp.48-54
Electronic Components and Technology Conference (ECTC) <61, 2011, Lake Buena Vista/Fla.>
English
Conference Paper
Fraunhofer IZM ()

Abstract
The constant drive towards further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding technologies and embedding of active components into printed circuit boards (Chip-in-Polymer) are two major packaging trends in this area. This paper describes the use of a novel S2iP (Stacked System in Package) interconnect technique using advanced molding process for multi chip embedding in combination with large area and low cost redistribution technology derived from printed circuit board manufacturing with a focus on integration of through mold vias for package stacking. The use of compression molding equipment with liquid or granular epoxy molding compounds for the targeted integration process flow is a new technology that has been especially developed to allow large area embedding of single chips but also of multiple chips or heterogeneous systems on wafer scale, typically 8” to 12”. Future developments will deal with panel sizes up to 470 × 370 mm2. The wiring of the embedded components in this novel type of SiP is done using PCB manufacturing technologies, i.e. a resin coated copper (RCC) film is laminated over the embedded components - whichever no matter which shape they are: a compression molded wafer or a larger rectangular area of a Molded Array Package (MAP). Interconnects are formed by laser drilling to die pads and electroplating - all of them making use of standard PCB processes. Thus, through vias which are standard features in PCB manufacturing and can be also integrated in the proposed process flow for mold embedding in combination with RCC based redistribution. Vias were drilled by laser or mechanically after RCC lamination and were metalized together with the vias for chip interconnection. Within this study different liquid and granular moldi- - ng compounds have been intensively evaluated on their processability. Via drilling process by laser and mechanical drilling is systematically developed and analyzed with focus on via diameter, pitch, mold thickness and molding compound composition and here especially on filler particle sizes and distribution. The feasibility of the entire process chain is demonstrated by fabrication of a Ball Grid Array (BGA) type of system package with two embedded dies and through mold vias allowing the stacking of these BGA packages. Finally, a technology demonstrator is described consisting of two BGAs stacked on each other and mounted on a base substrate enabling the electrical test of a daisy chain structure through the stacked module, allowing the evaluation of the technology and the applied processes.

: http://publica.fraunhofer.de/documents/N-180409.html