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Hierarchical simulation of process variations and their impact on circuits and systems: Results

 
: Lorenz, J.K.; Bär, E.; Clees, T.; Evanschitzky, P.; Jancke, R.; Kampen, C.; Paschen, U.; Salzig, C.P.J; Selberherr, S.

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IEEE transactions on electron devices 58 (2011), No.8, pp.2227-2234
ISSN: 0018-9383
English
Journal Article
Fraunhofer IISB ()
Fraunhofer IMS ()
Fraunhofer SCAI ()
Fraunhofer EAS ()
Fraunhofer ITWM ()
process variation; process simulation; device simulation; circuit simulation; system simulation; manufacturability; process modeling; semiconductor device modeling; sensitivity; yield

Abstract
Process variations increasingly challenge the manufacturability of advanced devices and the yield of integrated circuits. Technology computer-aided design (TCAD) has the potential to make key contributions to minimize this problem, by assessing the impact of certain variations on the device, circuit, and system. In this way, TCAD can provide the information necessary to decide on investments in the processing level or the adoption of a more variation tolerant process flow, device architecture, or design on circuit or chip level. Five Fraunhofer institutes joined forces to address these issues. Their own software tools, e.g., for lithography/topography simulation, mixed-mode device simulation, compact model extraction, and behavioral modeling, have been combined with commercial tools to est ablish a hierarchical system of simulators in order to analyze process variations from their source, e.g., in a lithography step, through device fabrication up to the circuit and system levels.

: http://publica.fraunhofer.de/documents/N-174864.html