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Through silicon via technology - processes and reliability for wafer-level 3D system integration

 
: Ramm, P.; Wolf, M.J.; Klumpp, A.; Wieland, R.; Wunderle, B.; Michel, B.; Reichl, H.

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IEEE Components, Packaging, and Manufacturing Technology Society; Electronic Components, Assemblies, and Materials Association:
58th Electronic Components and Technology Conference 2008. Proceedings. Vol.2 : Lake Buena Vista, FL, 27 - 30 May 2008
Piscataway, NJ: IEEE, 2008
ISBN: 978-1-4244-2230-2
pp.841-846
Electronic Components and Technology Conference (ECTC) <58, 2008, Lake Buena Vista/Fla.>
English
Conference Paper
Fraunhofer IZM ()
Fraunhofer IWM ()

Abstract
3D integration is a rapidly growing topic in the semiconductor industry that encompasses different types of technologies. The paper addresses one of the most promising technologies which uses through silicon vias (TSV) for interconnecting stacked devices on wafer-level to perform high density interconnects with a good electrical performance at the smallest form factor for 3D architectures. Fraunhofer IZM developed a post frontend 3D integration process, the so-called ICV-SLID technology based on metal bonding using solid-liquid-interdiffusion (SLID) soldering. The SLID metal system provides the mechanical and the electrical connection, both in one single step. The ICV-SLID fabrication process is well suited for the cost-effective production of both, high-performance applications (e.g. 3D microprocessor) and highly miniaturized multi-functional systems. The latter preferably in combination with wafer-level die stacking, as e.g. Thin Chip Integration (TCI) or SnAg-microbu mp technologies. The fabrication of distributed wireless sensor systems (e. g. e-CUBES®) is a typical example for the need of such mixed approaches.

: http://publica.fraunhofer.de/documents/N-173211.html