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EMC modeling and simulation on chiplevel

: Steinecke, T.; John, W.; Koehne, H.; Schmidt, M.

IEEE Electromagnetic Compatibility Society:
IEEE International EMC International Symposium, EMC 2001. Symposium record. Vol.2 : International Rende-Vous. Montréal, Canada, August 13 - 17, 2001
Piscataway: IEEE Operations Center, 2001
ISBN: 0-7803-6569-0
International Symposium on Electromagnetic Compatibility (EMC) <2001, Montreal>
Conference Paper
Fraunhofer IZM ()

Due to increasing demands for reduced electromagnetic emission on chip-level in combination with more complex circuits and faster design cycles, it is mandatory to spend effort on EMC models and simulation for chip design. In this paper a three-level approach, based on (1) testchip design and measurement, (2) RLC-extraction of supply system plus transistor netlist simulation, (3) behavioural models for simple gates and complex digital modules will be presented. Correlation between results of those three levels has to be established, and finally behavioural models for complete CMOS VLSI chips have to be derived and implemented in a simulation environment.