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Wafer Level Burn-In (WLBI) for flip chip applications

: Jung, E.; Aschenbrenner, R.; Wojakowski, D.; Reichl, H.

American Society of Mechanical Engineers -ASME-:
Advances in electronic packaging 2001. Vol.3 : Proceedings of IPACK '01. The Pacific Rim/ASME International Electronic Packaging Technical Conference and Exhibition, July 8 - 13, 2001, Kauai, Hawaii
ISBN: 0-7918-3540-5
Pacific Rim International, Intersociety Electronic Packaging Technical Business Conference and Exhibition <2001, Kauai>
Conference Paper
Fraunhofer IZM ()

The growing acceptance of flip chip technology in assembly and manufacturing of a broad scope of products is facing similar issues, as wirebonding for COB and MCM's before. Repair issues due to intrinsically defective dies, having passed standard electrical tests but no burn-in, tend to challenge the cost and performance benefits of bare die attach. Testing and burning-in of bare, unpackaged dies (yielding so called "Known Good Dies") requires sophisticated test equipment while providing only low throughput. Over the last decade, a number of wafer level bum in concepts have evolved, the majority of them focusing on IC's dedicated for wirebond use. Only few of them found their way into production so far. Flip Chip now requires a different approach, as the dies are not to be tested before, but after bumping. Test equipment and - processes do not lend themselves readily to this task. This paper presents a novel concept for wafer level burn in dedicated for the special need s of flip chips. Using a reusable burn-in substrate, only one step is needed to realize the electrical contacts for the burn in for wafers and the bumps for the flip chip. The technology developed is described and the identified issues are explained. Reliability tests of the burnt-in dice are given and compared to flip chips manufactured with standard bumping methods.