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Minimizing reflections and cross-talk in chip packages

 
: Ndip, I.; John, W.; Reich, H.

IEEE Components, Packaging, and Manufacturing Technology Society:
EPTC 2005, 7th Electronics Packaging Technology Conference
New York, NY: IEEE, 2005
ISBN: 0-7803-9578-6
ISBN: 0-7803-9579-4
pp.43-48
Electronics Packaging Technology Conference (EPTC) <7, 2005, Singapur>
English
Conference Paper
Fraunhofer IZM ()

Abstract
One of the main objectives of optimizing the performance of chip packages is to create electrically transparent interconnections between the chips in electronic systems. This performance optimization can only be achieved if signal integrity (SI) problems such as reflections and cross-talk that occur within the packages can be reduced to within acceptable limits. In this contribution, we present novel techniques used for the derivation of design rules to minimize reflections and cross-talk in chip packages. Examples of such design rules include the following: Using an optimal choice and design of bends on package traces as well as vias to minimize reflections and distortions; Considering the effects of technological tolerances at the beginning of the design cycle to prevent unexpected reflections; Using an optimal choice of substrate technology, as well as an optimal number and arrangement of power/ground interplane vias in the vicinity of sensitive signal paths, so as t o minimize cross-talk between package traces and vias, respectively.

: http://publica.fraunhofer.de/documents/N-173102.html