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Path tracing for injected parasitic noise into printed circuit boards
|IEEE Electromagnetic Compatibility Society:|
IEEE International Symposium on Electromagnetic Compatibility, EMC 2005. Proceedings. Vol.3 : 8 - 12 August 2005, Chicago, Illinois, USA
Piscataway, NJ: IEEE Operations Center, 2005
|International Symposium on Electromagnetic Compatibility (EMC) <2005, Chicago/Ill.>|
| Conference Paper|
|Fraunhofer IZM ()|
This paper presents an approach for tracing parasitic noise propagation paths in printed circuit boards. The approach allows the identification of the dominant paths transporting significant noise power from a peripheral connector pin to a sensitive device pin. The identification of these paths is performed in the frequency domain using scattering parameters and graph searching algorithms. The approach is combined with the harmonic balance technique for time domain analysis of the nonlinear components. The superposition of a limited number of extracted dominant noise propagation paths in both frequency-and time domain gives a good approximation of the total system response. The method can be used to improve the interconnect design before any physical implementation of the circuitry.