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3-D capacitive interconnections for wafer-level and die-level assembly

: Fazzi, A.; Magagni, L.; Mirandola, M.; Charlet, B.; Cioccio, L. di; Jung, E.; Canegallo, R.; Guerrieri, R.


IEEE journal of solid-state circuits 42 (2007), No.10, pp.2270-2281
ISSN: 0018-9200
Journal Article
Fraunhofer IZM ()

This paper presents a 3-D interconnection scheme based on capacitive coupling. We propose synchronous communication circuits, based on a precharge and transmission approach, that provide an optimization of interconnection sensitivity. Measurements on a 0.13 m CMOS implementation demonstrate working connections with an area occupation of 8 × 8 m2. Experimental results are presented for both die-to-die and wafer-to-wafer assembly techniques. They show a maximum communication bandwidth of 1.23 Gb/s, leading to a throughput per area of 19 Mb/s/m2 with an energy consumption of 0.14 mW/Gb/s. BER measurements demonstrate the reliability of these AC interconnections with no error on more than 1013 bits transmitted.