Fraunhofer-Gesellschaft

Publica

Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

Design study of the bump on flexible lead by FEA for wafer level packaging

 
: Eidner, I.; Wunderle, B.; Pan, K.L.; Wolf, M.J.; Ehrmann, O.; Reichl, H.

:

Institute of Electrical and Electronics Engineers -IEEE-:
10th International Conference on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2009 : Delft, Netherlands, 26 - 29 April 2009
New York, NY: IEEE, 2009
ISBN: 978-1-4244-4160-0
ISBN: 978-1-4244-4159-4
Art. 4938476
International Conference on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE) <10, 2009, Delft>
English
Conference Paper
Fraunhofer IZM ()

Abstract
The Bump on Flexible Lead (BoFL) is a chip-to substrate interconnect technology which uses flexible structures to accommodate the CTE mismatch between the chip and PCB substrate and consequently should be reliable without under fill. To achieve a high flexibility, the lead-free bump is located on a flexible lead. The flexible lead consists of a copper redistribution layer(RDL) embedded in a polyimide-bridge which is located over an air gap. Since the stress due to CTEmismatch is then accommodated within the flexible lead, the risk of solder fatigue decreases. The new failure risks are mainly related to fatigue of the copperRDL. Therefore a design study of the flexible lead by finite element analysis (FEA) was performed. The parameters investigated were the polyimide thickness, the thickness of the copper RDL and the shape of the copper RDL. The results obtained from the simulation study are useful to form design guidelines for enhanced board level reliability of the BoF L-WLP.

: http://publica.fraunhofer.de/documents/N-172998.html