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Value added packaging of microsystems

: Jung, E.

Courtois, B. ; IEEE Components, Packaging, and Manufacturing Technology Society; Circuits Multi-Projets -CMP-, Grenoble:
Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2010 : Seville, Spain, 5-7 May 2010; including the Conference on CAD, Design and Test and the Conference on Microfabrication, Integration and Packaging
Piscataway/NJ: IEEE, 2010
ISBN: 978-1-4244-6636-8
ISBN: 978-2-35500-011-9
Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP) <2010, Seville>
Conference Paper
Fraunhofer IZM ()

Packaging of Microsystems is one of the key technologies for success or failure of a product in the market. Performance aspects, reliability performance, cost and fabrication volume capability are among the factors governed by packaging - if not properly met, even a well designed component will not meet the market requirements. This paper targets to provide an overview on viable technologies for packaging specifically towards the suitability for microsystems with multiple individual components which need to operate seamlessly.