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Implementation of chip embedding processes for the creation of miniaturized system-in-packages

 
: Böttcher, Lars; Manessis, Dionysios; Ostmann, Andreas; Karaszkiewicz, Stefan; Aschenbrenner, Rolf; Lang, Klaus-Dieter

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Institute of Electrical and Electronics Engineers -IEEE-; VDE/VDI-Gesellschaft Mikroelektronik, Mikro- und Feinwerktechnik -GMM-:
3rd Electronics System Integration Technology Conference, ESTC 2010. Proceedings. Vol.1 : Berlin, Germany, 13 - 16 September 2010
New York, NY: IEEE, 2010
ISBN: 978-1-4244-8553-6
ISBN: 978-1-4244-8554-3
pp.98-103
Electronics System Integration Technology Conference (ESTC) <3, 2010, Berlin>
English
Conference Paper
Fraunhofer IZM ()

Abstract
This paper details the newest developments in chip embedding technologies for chips with a pitch of 100m. The technology developed in this study does not necessitate expensive redistribution layers for enlarging the pad pitch. Embedding of small pitch chips has been realised with concurrent developments in accurate chip positioning, plating methods and chemistries and ultra fine line patterning. The results in this paper show the emergence of a new prototype Embedded chip-QFN package with contact pads at 400m pitch and a total number of 84I/Os with dimensions of 10mmx5mm. The embedded chip in the QFN package is 5mmx5mm in size and has a peripheral pad configuration at 100m pitch. All Embedded chip-QFN packages have been manufactured in 10"x14" panels at prototype level. This paper also presents developments in semi-additive processing up to 15m LIS copper structuring on very thin copper foils. Package reliability studies have shown excellent resin/chip adhesion and good thermo-mechanical stability of embedded interfaces for all tests.

: http://publica.fraunhofer.de/documents/N-172922.html